Electronic and semiconductor components are used in ever increasing numbers of consumer and commercial electronic products, communications products and data-exchange products. As the demand for consumer and commercial electronics increases, there is also a demand for those same products to become smaller and more portable for the consumers and businesses.
As a result of the size decrease in these products, the components that comprise the products must also become smaller and/or thinner. Examples of some of those components that need to be reduced in size or scaled down are microelectronic chip interconnections, semiconductor chip components, resistors, capacitors, printed circuit or wiring boards, wiring, keyboards, touch pads, and chip packaging.
When electronic and semiconductor components are reduced in size or scaled down, any defects that are present in the larger components are going to be exaggerated in the scaled down components. Thus, the defects that are present or could be present in the larger component should be identified and corrected, if possible, before the component is scaled down for the smaller electronic products.
In order to identify and correct defects in electronic, semiconductor and communications components, the components, the materials used and the manufacturing processes for making those components should be broken down and analyzed. Electronic, semiconductor and communication/data-exchange components are composed, in some cases, of layers of materials, such as metals, metal alloys, ceramics, inorganic materials, polymers, or organometallic materials. The layers of materials are often thin (on the order of less than a few tens of angstroms in thickness). In order to improve on the quality of the layers of materials, the process of forming the layer—such as physical vapor deposition of a metal or other compound—should be evaluated and, if possible, improved.
In addition to improving the quality of the layers of materials that are deposited or applied to surfaces, users also want to improve the length of time components, such as sputtering targets, can be used before their effective lifetime diminishes. In other words, users are looking to get the most out of starting materials, such as those found on a sputtering target, in order to decrease costs and maintenance time.
In a typical vapor deposition process, such as physical vapor deposition (PVD), a sample or target is bombarded with an energy source such as a plasma, laser or ion beam, until atoms are released into the surrounding atmosphere. The atoms that are released from the sputtering target travel towards the surface of a substrate (typically a silicon wafer) and coat the surface forming a thin film or layer of a material. Atoms are released from the sputtering target 10 and travel on an ion/atom path 30 towards the wafer or substrate 20, where they are deposited in a layer.
When a sputtering target is initially utilized, there is a period of time called the “burn-in time” where the surface of the target is “cleaned” of any contaminants or surface deformities in order to produce stable films on surfaces. This burn-in time is usually measured in kilowatt hours. Depending on the method of manufacturing and finishing the sputtering targets, burn-in time can be severely impacted because of surface imperfections and debris. One of the problems with a long burn-in time is that this extended time impacts productivity and overall cost of ownership of the sputtering targets.
U.S. Pat. No. 6,030,514 issued to Dunlop et al. addresses the extended burn-in time problem by utilizing non-mechanical methods to clean and polish the surface of targets before covering the target with a metal enclosure and optionally a passivating barrier layer. The metallic enclosure is designed to help reduce the burn-in time, along with the method of cleaning step. The metallic enclosure or metal layer is an additional step in the process, which can add cost and production time to the product. In this patent, the methods of laser ablation and chemical etching are utilized to remove surface contaminants or bulk material from the surface; however, a portion of the surface is removed during either or both treatments. It would be desirable to merely reduce the overall crystallographic mis-orientation of the surface through annealing and to create the fine network of rounded peaks and valleys that cause burn-in to occur at a faster rate than normal without changing the weight of target.
U.S. Pat. No. 6,153,315 discloses methods of polishing and etching the target surface to reduce burn-in, but this patent cites minimization of the surface roughness as a critical aspect of the invention. In reality, surface roughness alone has nothing to do with the sputter performance of the target, since a fully burned-in target will have a very high surface roughness on the order of the average grain size of the target. The disclosure suggests that the surface roughness needs to be less than 1 micron Ra. In reality, the target should perform well with a surface roughness as high at 50 microns Ra (assuming a nominal 50 micron grain size), as long as the surface protuberances are not sharp enough to introduce arcing.
U.S. Pat. No. 6,284,111 is similar to U.S. Pat. No. 6,153,315, but claims a surface roughness range of 0.4 to 4 microns. The target with the surface described in this patent can potentially work to reduce burn-in, but only if combined with a method such as that disclosed in U.S. Pat. No. 6,331,233 where the bulk of the target has a uniform texture. Targets containing bands of strong preferred orientation can still exhibit very long burn-in times, sometimes up to one fifth of the total target life, even if the surface of the target is free of crystallographic damage.
U.S. Pat. No. 5,632,869 discloses the use of a pre-texturizing method such as machining a grooved pattern into the surface of the target in order to artificially roughen the target surface to mimic the high roughness of a sputtered surface, modify the electric field lines and draw the plasma closer to the surface to increase the sputter rate. Unfortunately, by machining grooves into the target surface, the machining action will propagate crystallographic damage deeper below the surface of the target than flat machining would do. Distortion of the crystal lattice can be more than 3 times the depth of the machine cut. A depth of 0.05 millimeters, as disclosed in the patent can mean an increased sub-surface damage depth of 150 microns or 0.15 mm (generally, three times the depth) or more, which can have the effect of actually prolonging burn-in time rather than reducing it. Chemical etching alone would not distort the crystal lattice, but achieving the cited roughening action through chemical etching would likely require an etch chemistry harsh enough to cause deep pitting, which would result in sharp edges on the target surface and in turn encourage arcing and subsequent particle generation.
U.S. Patent Publication 2005/0040030 also discusses reducing the burn-in time of a target by dry treating the sputtering target using a sputtering ion plasma, however, this publication reduces the burn-in time of the target in a vacuum chamber, as opposed to pre-treating the surface material. The utilization of a vacuum chamber can add costs and maintenance time to the production of the target.
U.S. Patent Publication 2007/0215463 discloses similar subject matter to the other patents and patent applications described herein—and that is utilizing a pre-conditioning method to remove part of the sputtering target surface, but there is no discussion regarding heat-treating the surface material in order to melt it and thereby affect the crystallographic orientation without removing material from the surface. As a matter of fact, this publication discloses annealing the surface of a target, and suggests that the temperature ranges from 400-1000° C., however, this process is in no way designed to melt the surface material of the target, because it is significantly lower than the melting point of many desirable materials, such as tantalum, which has a melting point above 2000° C.
To this end, it would be desirable to produce a sputtering target that a) can be produced with a minimal amount of residual surface damage, b) can be produced to minimize burn-in times by at least 10% as compared to conventional sputtering targets, c) can be produced to minimize surface and near surface distortions of the crystallographic orientation, d) can be produced with a uniform, band-free crystallographic orientation, and e) can be produced efficiently.